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Burr Brown Products from Texas Instruments
DSD1792A
SLES106 - FEBRUARY 2004
24 BIT, 192 kHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL TO ANALOG CONVERTER
FEATURES D Supports Both DSD and PCM Formats D 24-Bit Resolution D Analog Performance:
- Dynamic Range: - 132 dB (9 V rms, Mono) - 129 dB (4.5 V rms, Stereo) - 127 dB (2 V rms, Stereo) - THD+N: 0.0004% Differential Current Output: 7.8 mA p-p 8x Oversampling Digital Filter: - Stop-Band Attenuation: -130 dB - Pass-Band Ripple: 0.00001 dB Sampling Frequency: 10 kHz to 200 kHz System Clock: 128, 192, 256, 384, 512, or 768 fS With Autodetect Accepts 16-, 20-, and 24-Bit Audio Data PCM Data Formats: Standard, I2S, and Left-Justified Optional Interface to External Digital Filter or DSP Available TDMCA Interface Available User-Programmable Mode Controls: - Digital Attenuation: 0 dB to -120 dB, 0.5 dB/Step - Digital De-Emphasis - Digital Filter Rolloff: Sharp or Slow - Soft Mute Dual Supply Operation: - 5 V Analog, 3.3 V Digital 5-V Tolerant Digital Inputs
D Small 28-Lead SSOP Package, Lead-Free
Product
APPLICATIONS D D D D D D D
A/V Receivers SACD Player DVD Players HDTV Receivers Car Audio Systems Digital Multi-Track Recorders Other Applications Requiring 24-Bit Audio
D D D D D D D D D
DESCRIPTION
The DSD1792A is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI's advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1792A provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1792A accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1792A also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port, which supports register write and readback functions. The DSD1792A also supports the time-division-multiplexed command and audio (TDMCA) data format.
D D
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
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ORDERING INFORMATION
PRODUCT DSD1792ADB PACKAGE 28-lead SSOP PACKAGE CODE 28DB OPERATION TEMPERATURE RANGE -25C to 85C PACKAGE MARKING DSD1792A ORDERING NUMBER DSD1792ADB DSD1792ADBR TRANSPORT MEDIA Tube Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) DSD1792A Supply voltage VCC1, VCC2L, VCC2R VDD -0.3 V to 6.5 V -0.3 V to 4 V 0.1 V 0.1 V -0.3 V to 6.5 V -0.3 V to (VDD + 0.3 V) < 4 V -0.3 V to (VCC + 0.3 V) < 6.5 V 10 mA -40C to 125C -55C to 150C 150C 260C, 5 s 250C
Supply voltage differences: VCC1, VCC2L and VCC2R Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R and DGND PLRCK, PDATA, PBCK, SCK, RST, MS(2), MDI, MC, DSDL(2), DSDR(2), DBCK Digital input voltage DSDL(3), DSDR(3), MS(3), MDO Analog input voltage Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (IR reflow, peak)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input mode (3) Output mode
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted DSD1792ADB PARAMETER RESOLUTION DATA FORMAT (PCM Mode) Audio data interface format Audio data bit length Audio data format fS Sampling frequency System clock frequency DATA FORMAT (DSD Mode) Audio data interface format Audio data bit length fS Sampling frequency System clock frequency 2.8224 DSD (direct stream digital) 1 Bit 2.8224 11.2896 MHz MHz Standard, I2S, left justified 16-, 20-, 24-bit selectable MSB first, 2s complement 10 200 kHz 128, 192, 256, 384, 512, 768 fS TEST CONDITIONS MIN TYP 24 MAX UNIT Bits
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ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted DSD1792ADB PARAMETER DIGITAL INPUT/OUTPUT Logic family VIH VIL IIH IIL VOH VOL Input logic level Input logic current Output logic level VIN = VDD VIN = 0 V IOH = -2 mA IOL = 2 mA 2.4 0.4 10 -10 0.0004% 0.0008% 0.0015% 123 127 127 127 123 127 127 127 120 123 122 120 1 0.0004% 0.0008% 0.0015% 129 129 129 129 129 129 124 123 121 dB dB dB dB dB dB dB 0.0008% TTL compatible 2 0.8 10 -10 Vdc A Vdc A TEST CONDITIONS MIN TYP MAX UNIT
IOHZ High-impedance output logic current(1) IOLZ
VOUT = VDD VOUT = 0 V DYNAMIC PERFORMANCE (PCM MODE, 2-V RMS OUTPUT) (2)(3) THD+N at VOUT = 0 dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz Channel separation fS = 44.1 kHz fS = 96 kHz
fS = 192 kHz Level Linearity Error VOUT = -120 dB DYNAMIC PERFORMANCE (PCM Mode, 4.5-V RMS Output) (2)(4) THD+N at VOUT = 0 dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz Channel separation fS = 44.1 kHz fS = 96 kHz fS = 192 kHz
(1) Pin 13 (MDO) (2) Filter condition: THD+N: 20-Hz HPF, 20-kHz apogee LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging mode. (3) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 33. (4) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 34.
Audio Precision and System Two are trademarks of Audio Precision, Inc. Other trademarks are the property of their respective owners. 3
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ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted DSD1792ADB PARAMETER DYNAMIC PERFORMANCE (MONO MODE) (1)(2) THD+N at VOUT = 0 dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz DSD MODE DYNAMIC PERFORMANCE (1) (3) (44.1 kHz, 64 FS) THD+N at FS Dynamic range Signal-to-noise ratio ANALOG OUTPUT Gain error Gain mismatch, channel-to-channel Bipolar zero error Output current Center current DIGITAL FILTER PERFORMANCE De-emphasis error FILTER CHARACTERISTICS-1: SHARP ROLLOFF Pass band Stop band Pass-band ripple Stop-band attenuation Delay time FILTER CHARACTERISTICS-2: SLOW ROLLOFF Pass band Stop band Pass-band ripple Stop-band attenuation Delay time Stop band = 0.732 fS -100 18/fS 0.04 dB -3 dB 0.732 fS 0.001 dB dB 0.254 fS 0.46 fS Stop band = 0.546 fS -130 55/fS 0.00001 dB -3 dB 0.546 fS 0.00001 dB dB s 0.454 fS 0.49 fS 0.004 dB At BPZ Full scale (0 dB) At BPZ -6 -3 -2 2 0.5 0.5 7.8 -6.2 6 3 2 % of FSR % of FSR % of FSR mA p-p mA 4.5 V rms -60 dB, EIAJ, A-weighted EIAJ, A-weighted 0.0005% 128 128 dB dB 0.0004% 0.0008% 0.0015% 132 132 132 132 132 132 dB dB TEST CONDITIONS MIN TYP MAX UNIT
s (1) Filter condition: THD+N: 20-Hz HPF, 20-kHz apogee LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging mode. (2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 34. (3) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 35.
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ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted DSD1792ADB PARAMETER POWER SUPPLY REQUIREMENTS VDD VCC1 VCC2L VCC2R IDD Supply current (1) ICC fS = 44.1 kHz fS = 96 kHz fS = 192 kHz fS = 44.1 kHz fS = 96 kHz fS = 192 kHz Power dissipation (1) TEMPERATURE RANGE Operation temperature JA Thermal resistance (1) Input is BPZ data. 28-pin SSOP -25 100 85 C C/W fS = 44.1 kHz fS = 96 kHz fS = 192 kHz 12 23 45 33 35 37 205 250 335 250 mW 40 mA 15 mA 3 Voltage range 4.75 3.3 5 3.6 5.25 Vdc Vdc TEST CONDITIONS MIN TYP MAX UNIT
PIN ASSIGNMENTS
DSD1792A (TOP VIEW)
DSDL DSDR DBCK PLRCK PDATA PBCK SCK DGND VDD MS MDI MC MDO RST
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC2L AGND3L IOUTL- IOUTL+ AGND2 VCC1 VCOML VCOMR IREF AGND1 IOUTR- IOUTR+ AGND3R VCC2R
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Terminal Functions
TERMINAL NAME AGND1 AGND2 AGND3L AGND3R DBCK DGND DSDL DSDR IOUTL+ IOUTL- IOUTR+ IOUTR- IREF MC MDI MDO MS PBCK PDATA PLRCK RST SCK VCC1 VCC2L VCC2R VCOML PIN 19 24 27 16 3 8 1 2 25 26 17 18 20 12 11 13 10 6 5 4 14 7 23 28 15 22 I/O - - - - I - I/O I/O O O O O - I I O I/O I I I I I - - - - Analog ground (internal bias) Analog ground (internal bias) Analog ground (L-channel DACFF) Analog ground (R-channel DACFF) Bit clock input for DSD modes (1) Digital ground L-channel audio data input when in DSD and external DF modes PCM-mode zero flag for L-channel when in zero-flag output mode(2) R-channel audio data input when in DSD and external DF modes PCM-mode zero flag for R-channel when in zero-flag output mode (2) L-channel analog current output + L-channel analog current output - R-channel analog current output + R-channel analog current output - Output current reference bias pin Mode control clock input(1) Mode control data input (1) Mode control readback data output (3) Mode control chip-select input(2) Bit clock input. Connected to GND in DSD mode (1) Serial audio data input for PCM-format operation (1) Left and right clock (fS) input for PCM-format operation. WDCK clock input for external DF mode. Connected to GND for DSD mode (1) Reset(1) System clock input (1) Analog power supply, 5 V Analog power supply (L-channel DACFF), 5 V Analog power supply (R-channel DACFF), 5 V L-channel internal bias decoupling pin DESCRIPTIONS
VCOMR 21 - R-channel internal bias decoupling pin VDD 9 - Digital power supply, 3.3 V (1) Schmitt-trigger input, 5-V tolerant (2) Schmitt-trigger input and output. 5-V tolerant input, and CMOS output (3) 3-state output
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FUNCTIONAL BLOCK DIAGRAM
DBCK DSDL DSDR Audio Data Input I/F 8 Oversampling Digital Filter and Function Control Function Control I/F Current Segment DAC IOUTL+ IOUTL- VOUTL
PLRCK PBCK PDATA
VCOML Advanced Segment DAC Modulator Bias and Vref IREF VCOMR
I/V and Filter
RST
MDO MDI MC MS Current Segment DAC
IOUTR- VOUTR IOUTR+ I/V and Filter
System Clock Manager
Power Supply
AGND3L
AGND3R
AGND1
AGND2
VCC2L
VCC2R
DGND
VCC1
SCK
VDD
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TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
Digital Filter Response
AMPLITUDE vs FREQUENCY
0 2 0.00002
AMPLITUDE vs FREQUENCY
-50 Amplitude - dB
1 0.00001 Amplitude - dB
-100
0
-150
-1 -0.00001
-200 0 1 2 Frequency [x fS] 3 4
-2 -0.00002 0.0
0.1
0.2
0.3
0.4
0.5
Frequency [x fS]
Figure 1. Frequency Response, Sharp Rolloff
AMPLITUDE vs FREQUENCY
0
Figure 2. Pass-Band Ripple, Sharp Rolloff
AMPLITUDE vs FREQUENCY
0 -2 -4
-50 -6 Amplitude - dB Amplitude - dB 0 1 2 Frequency [x fS] 3 4 -8 -10 -12 -14 -150 -16 -18 -200 -20 0.0
-100
0.1
0.2
0.3
0.4
0.5
0.6
Frequency [x fS]
Figure 3. Frequency Response, Slow Rolloff
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Figure 4. Transition Characteristics, Slow Rolloff
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De-Emphasis Error
DE-EMPHASIS LEVEL vs FREQUENCY
0 fS = 32 kHz 15 0.015 -2 De-Emphasis Level - dB De-Emphasis Error - dB 10 0.010 5 0.005 0 -5 -0.005 -10 -0.010 -15 -0.015 -10 0 2 4 6 8 10 12 14 f - Frequency - kHz -20 -0.020 0 2 4 6 8 10 12 14 f - Frequency - kHz 20 0.020 fS = 32 kHz
DE-EMPHASIS ERROR vs FREQUENCY
-4
-6
-8
Figure 5
DE-EMPHASIS LEVEL vs FREQUENCY
0 fS = 44.1 kHz 15 0.015 -2 De-Emphasis Level - dB De-Emphasis Error - dB 10 0.010 5 0.005 0 -5 -0.005 -10 -0.010 -15 -0.015 -10 0 2 4 6 8 10 12 14 16 18 20 f - Frequency - kHz -20 -0.020 0 2 4 20 0.020
Figure 6
DE-EMPHASIS ERROR vs FREQUENCY
fS = 44.1 kHz
-4
-6
-8
6
8
10
12
14
16
18
20
f - Frequency - kHz
Figure 7
Figure 8
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De-Emphasis Error (Continued)
DE-EMPHASIS LEVEL vs FREQUENCY
0 fS = 48 kHz 15 0.015 -2 De-Emphasis Level - dB De-Emphasis Error - dB 10 0.010 5 0.005 0 -5 -0.005 -10 -0.010 -15 -0.015 -10 0 2 4 6 8 10 12 14 16 18 20 22 f - Frequency - kHz -20 -0.020 0 2 4 6 8 10 12 14 16 18 20 22 f - Frequency - kHz 20 0.020 fS = 48 kHz
DE-EMPHASIS ERROR vs FREQUENCY
-4
-6
-8
Figure 9
Figure 10
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ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE
0.01 THD+N - Total Harmonic Distortion + Noise - % 132
DYNAMIC RANGE vs SUPPLY VOLTAGE
130 fS = 96 kHz Dynamic Range - dB 128 fS = 192 kHz 126 fS = 48 kHz
0.001
fS = 192 kHz
fS = 96 kHz
124 fS = 48 kHz 0.0001 4.50 122 4.50
4.75
5.00
5.25
5.50
4.75
5.00
5.25
5.50
VCC - Supply Voltage - V
VCC - Supply Voltage - V
Figure 11
SIGNAL-to-NOISE RATIO vs SUPPLY VOLTAGE
132 130
Figure 12
CHANNEL SEPARATION vs SUPPLY VOLTAGE
SNR - Signal-to-Noise Ratio - dB
130 fS = 96 kHz 128 fS = 48 kHz 126 fS = 192 kHz Channel Separation - dB
128
126
fS = 96 kHz fS = 192 kHz fS = 48 kHz
124
124
122
122 4.50
4.75
5.00
5.25
5.50
120 4.50
4.75
5.00
5.25
5.50
VCC - Supply Voltage - V
VCC - Supply Voltage - V
Figure 13
Figure 14
NOTE: PCM mode, TA = 25C, VDD = 3.3 V, measurement circuit is Figure 34 (VOUT = 4.5 V rms). 11
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Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE
0.01 THD+N - Total Harmonic Distortion + Noise - % 132
DYNAMIC RANGE vs FREE-AIR TEMPERATURE
130 Dynamic Range - dB
fS = 96 kHz fS = 48 kHz
128
fS = 192 kHz
0.001
fS = 192 kHz
126
fS = 96 kHz fS = 48 kHz
124
0.0001 -50
-25
0
25
50
75
100
122 -50
-25
0
25
50
75
100
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 15
SIGNAL-to-NOISE RATIO vs FREE-AIR TEMPERATURE
132 130
Figure 16
CHANNEL SEPARATION vs FREE-AIR TEMPERATURE
SNR - Signal-to-Noise Ratio - dB
130 Channel Separation - dB fS = 96 kHz 128 fS = 192 kHz fS = 48 kHz 126
128
126 fS = 48 kHz 124 fS = 192 kHz fS = 96 kHz 122
124
122 -50
-25
0
25
50
75
100
120 -50
-25
0
25
50
75
100
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 17
Figure 18
NOTE: PCM mode, VCC = 5 V, VDD = 3.3 V, measurement circuit is Figure 34 (VOUT = 4.5 V rms). 12
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AMPLITUDE vs FREQUENCY
0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 2 4 6 8 10 12 14 16 18 20 f - Frequency - kHz 0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 10 20 30
AMPLITUDE vs FREQUENCY
Amplitude - dB
40
50
60
70
80
90 100
f - Frequency - kHz
Figure 19. -60-db Output Spectrum, BW = 20 kHz
Figure 20. -60-db Output Spectrum, BW = 100 kHz
NOTE: PCM mode, fS = 48 kHz, 32,768 point 8 average, TA = 25C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 34.
TOTAL HARMONIC DISTORTION + NOISE vs INPUT LEVEL
10 THD+N - Total Harmonic Distortion + Noise - %
1
0.1
0.01
0.001
0.0001 -100
-80
-60
-40
-20
0
Input Level - dBFS
Figure 21. THD+N vs Input Level, PCM Mode
NOTE: PCM mode, fS = 48 kHz, TA = 25C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 34.
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AMPLITUDE vs FREQUENCY
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 2 4 6 8 10 12 14 16 18 20 f - Frequency - kHz
Figure 22. -60-dB Output Spectrum, DSD Mode
NOTE: DSD mode (FIR-4), 32,768 point 8 average, TA = 25C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 35.
AMPLITUDE vs FREQUENCY
-130 -133 -136 -139 Amplitude - dB -142 -145 -148 -151 -154 -157 -160 0 2 4 6 8 10 12 14 16 18 20 f - Frequency - kHz
Figure 23. -150-dB Output Spectrum, DSD Mono Mode
NOTE: DSD mode (FIR-4), 32,768 point 8 average, TA = 25C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 35. 14
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SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The DSD1792A requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The DSD1792A has a system clock detection circuit that automatically senses if the system clock is operating between 128 fS and 768 fS. Table 1 shows examples of system clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as 128 fS, the system clock frequency is over 256 fS. Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. One of the Texas Instruments' PLL1700 family of multiclock generators is an excellent choice for providing the DSD1792A system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY 32 kHz 44.1 kHz 48 kHz 96 kHz 192 kHz SYSTEM CLOCK FREQUENCY (FSCK) (MHz) 128 fS 4.096 5.6488 6.144 12.288 24.576 192 fS 6.144 8.4672 9.216 18.432 36.864 256 fS 8.192 11.2896 12.288 24.576 49.152 384 fS 12.288 16.9344 18.432 36.864 73.728 512 fS 16.384 22.5792 24.576 49.152 (1) 768 fS 24.576 33.8688 36.864 73.728 (1)
(1) This system clock rate is not supported for the given sampling frequency. t(SCKH) H System Clock (SCK) L t(SCKL) t(SCY) MIN 13 0.4t (SCY) 0.4t (SCY) MAX UNITS ns ns ns 0.8 V 2.0 V
PARAMETERS t(SCY) System clock pulse cycle time t(SCKH) System clock pulse duration, HIGH t(SCKL) System clock pulse duration, LOW
Figure 24. System Clock Input Timing
Power-On and External Reset Functions
The DSD1792A includes a power-on reset function. Figure 25 shows the operation of this function. With VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. After the initialization period, the DSD1792A is set to its default reset state, as described in the MODE CONTROL REGISTERS section of this data sheet. The DSD1792A also includes an external reset capability using the RST input (pin 14). This allows an external controller or master reset circuit to force the DSD1792A to initialize to its default reset state. Figure 26 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. Operation of the external reset is the same as that of the power-on reset. The external reset is especially useful in applications where there is a delay between the DSD1792A power up and system clock activation.
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VDD 2.4 V (Max) 2.0 V (Typ) 1.6 V (Min)
Reset Internal Reset
Reset Removal
1024 System Clocks System Clock
Figure 25. Power-On Reset Timing
RST (Pin 14)
50 % of VDD
t(RST) Reset Internal Reset 1024 System Clocks System Clock PARAMETERS t(RST) Reset pulse duration, LOW MIN 20 MAX UNITS ns Reset Removal
Figure 26. External Reset Timing
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AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes PLRCK (pin 4), PBCK (pin 6), and PDATA (pin 5). PBCK is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of the audio interface. Serial data is clocked into the DSD1792A on the rising edge of PBCK. PLRCK is the serial audio left/right word clock. The DSD1792A requires the synchronization of PLRCK and the system clock, but does not need a specific phase relation between PLRCK and the system clock. If the relationship between PLRCK and the system clock changes more than 6 PBCK, internal operation is initialized within 1/fS and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the system clock is completed.
PCM Audio Data Formats and Timing
The DSD1792A supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0], in control register 18. The default data format is 24-bit I2S. All formats require binary 2s complement, MSB-first audio data. Figure 27 shows a detailed timing diagram for the serial audio interface.
PLRCK t(BCH) PBCK t(BCY) PDATA t(DS) PARAMETERS t(BCY) t(BCL) t(BCH) t(BL) t(LB) t(DS) t(DH) -- PBCK pulse cycle time PBCK pulse duration, LOW PBCK pulse duration, HIGH PBCK rising edge to PLRCK edge PLRCK edge to PBCK rising edge PDATA Setup time PDATA hold time PLRCK clock data t(DH) MIN 70 30 30 10 10 10 10 MAX UNITS ns ns ns ns ns ns ns t(BL) 50% of VDD t(BCL) t(LB) 50% of VDD 50% of VDD
50% 2 bit clocks
Figure 27. Timing of Audio Interface
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(1) Standard Data Format (Right-Justified); L-Channel = HIGH, R-Channel = LOW
1/fS PLRCK L-Channel R-Channel
PBCK
Audio Data Word = 16-Bit PDATA 14 15 16 1 2 MSB Audio Data Word = 20-Bit PDATA 18 19 20 1 2 MSB Audio Data Word = 24-Bit PDATA 22 23 24 1 2 MSB 23 24 LSB 1 2 23 24 19 20 LSB 1 2 19 20 15 16 LSB 1 2 15 16
(2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS PLRCK L-Channel R-Channel
PBCK Audio Data Word = 24-Bit PDATA 1 2 MSB 23 24 LSB 1 2 23 24 1 2
(3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
PLRCK L-Channel 1/fS R-Channel
PBCK
Audio Data Word = 16-Bit PDATA 1 2 MSB Audio Data Word = 24-Bit PDATA 1 2 MSB 23 24 LSB 1 2 23 24 1 2 15 16 LSB 1 2 15 16 1 2
Figure 28. Audio Data Input Formats
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External Digital Filter Interface and Timing
The DSD1792A supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which allows the use of an external digital filter. External filters include the Texas Instruments' DF1704 and DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor. In the external DF mode, PLRCK (pin 4), PBCK (pin 6) and PDATA (pin 5) are defined as WDCK, the word clock; BCK, the bit clock; and DATA, the monaural data, respectively. The external digital filter interface is selected by using the DFTH bit of control register 20, which functions to bypass the internal digital filter of the DSD1792A. When the DFMS bit of control register 19 is set, the DSD1792A can process stereo data. In this case, DSDL (pin 1) and DSDR (pin 2) are defined as L-channel data and R-channel data, respectively. Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet.
Direct Stream Digital (DSD) Format Interface and Timing
The DSD1792A supports the DSD-format interface operation, which includes out-of-band noise filtering using an internal analog FIR filter. The DSD-format interface consists of a 3-wire synchronous serial port, which includes DBCK (pin 3), DSDL (pin 1), and DSDR (pin 2). DBCK is the serial bit clock. DSDL and DSDR are L-channel and R-channel DSD data input, respectively. They are clocked into the DSD1792A on the rising edge of DBCK. PLRCK (pin 4) and PBCK (pin 6) should be connected to GND in the DSD mode. The DSD-(DSD mode) format interface is activated by setting the DSD bit of control register 20. Detailed information for the DSD mode is provided in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data sheet.
TDMCA Interface
The DSD1792A supports the time-division-multiplexed command and audio (TDMCA) data format to enable control of and communication with a number of external devices over a single serial interface. Detailed information for the TDMCA format is provided in the TDMCA Format section of this data sheet.
FUNCTION DESCRIPTIONS Serial Control Interface
The serial control interface is a 4-wire synchronous serial port, which operates asynchronously with the serial audio interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data output, used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers; MC is the bit clock, used to shift data in and out of the control port, and MS is the mode control enable, used to enable the internal mode register access.
Register Read/Write Operation
All read/write operations for the serial control port use 16-bit data words. Figure 29 shows the control data word format. The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For read operations, the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that set the register index (or address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0] or to be read from, the register specified by IDX[6:0]. Figure 30 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1 state until a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on MDO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the indexed-mode control register during the write operation. To write or read subsequent data, MS must be set to 1 once.
MSB R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 LSB D0
Register Index (or Address)
Register Data
Figure 29. Control Data Word Format for MDI
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MS
MC
MDI
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MDO
High Impedance
D7
D6
D5
D4
D3
D2
D1
D0
When Read Mode is Instructed NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14-8 are used for the register address. Bits 7-0 are used for register data.
Figure 30. Serial Control Format
t(MHH) MS t(MSS) t(MCH) MC t(MCY) MDI t(MDS) t(MDH) MDO 50% of VDD LSB 50% of VDD t(MCL) t(MSH) 50% of VDD 50% of VDD
t(MOS)
PARAMETER t(MCY) t(MCL) t(MCH) t(MHH) t(MSS) t(MSH) t(MDH) t(MDS) MC pulse cycle time MC low-level time MC high-level time MS high-level time MS falling edge to MC rising edge MS hold time(1) MDI hold time MDI setup time
MIN 100 40 40 80 15 15 15 15
MAX
UNITS ns ns ns ns ns ns ns ns
t(MOS) MC falling edge to MDO stable (1) MC rising edge for LSB to MS rising edge
30
ns
Figure 31. Control Interface Timing
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MODE CONTROL REGISTERS
User-Programmable Mode Controls
The DSD1792A includes a number of user-programmable functions which are accessed via mode control registers. The registers are programmed using the serial control interface, which was previously discussed in this data sheet. Table 2 lists the available mode-control functions, along with their default reset conditions and associated register index.
Table 2. User-Programmable Function Controls
FUNCTION Digital attenuation control 0 dB to -120 dB and mute, 0.5 dB/step Attenuation load control--Disabled, enabled Input audio data format selection 16-, 20-, 24-bit standard (right-justified) format 24-bit MSB-first left-justified format 16-/24-bit I2S format Sampling rate selection for de-emphasis Disabled, 44.1 kHz, 48 kHz, 32 kHz De-emphasis control--Disabled, enabled Soft mute control--Mute disabled, enabled Output phase reversal--Normal, reverse Attenuation speed selection x1 fS, x(1/2) fS, x(1/4) fS, x(1/8) fS DAC operation control--Enabled, disabled Zero flag pin operation control DSD data input, zero flag output Stereo DF bypass mode select Monaural, stereo Digital filter rolloff selection Sharp rolloff, slow rolloff Infinite zero mute control Disabled, enabled System reset control Reset operation, normal operation DSD interface mode control DSD enabled, disabled Digital-filter bypass control DF enabled, DF bypass Monaural mode selection Stereo, monaural Channel selection for monaural mode data L-channel, R-channel Delta-sigma oversampling rate selection x64 fS, x128 fS, x32 fS PCM zero output enable DSD zero output enable Function available only for read Zero detection flag Not zero, zero detected Not zero = 0 Zero detected = 1 Register 22 ZFGL (for L-ch) ZFGR (for R-ch) yes yes yes yes yes 0 dB Attenuation disabled 24-bit I2S format DEFAULT REGISTER Register 16 Register 17 Register 18 Register 18 BIT ATL[7:0] (for L-ch) ATR[7:0] (for R-ch) ATLD FMT[2:0] PCM yes yes yes yes DSD DF BYPASS
De-emphasis disabled De-emphasis disabled Mute disabled Normal x1 fS DAC operation enabled DSD data input Monaural Sharp rolloff Disabled Normal operation Disabled DF enabled Stereo L-channel x64 fS Enabled Disabled
Register 18 Register 18 Register 18 Register 19 Register 19 Register 19 Register 19 Register 19 Register 19 Register 19 Register 20 Register 20 Register 20 Register 20 Register 20 Register 20 Register 21 Register 21
DMF[1:0] DME MUTE REV ATS[1:0] OPE ZOE DFMS FLT INZD SRST DSD DFTH MONO CHSL OS[1:0] PCMZ DZ[1:0]
yes yes yes yes yes yes yes
yes(1)
yes
yes
yes
yes yes yes
yes yes yes yes yes yes yes yes yes yes yes yes yes yes(2) yes yes yes yes yes yes
Device ID (at TDMCA) -- Register 23 ID[4:0] (1) When in DSD mode, DMF[0:1] is defined as DSD filter (analog FIR) performance selection. (2) When in DSD mode, OS[0:1] is defined as DSD filter (analog FIR) operation rate selection.
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Register Map
The mode control register map is shown in Table 3. Registers 16-21 include an R/W bit, which determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.
Table 3. Mode Control Register Map
B15 Register 16 Register 17 Register 18 Register 19 Register 20 Register 21 Register 22 Register 23 R/W R/W R/W R/W R/W R/W R R B14 0 0 0 0 0 0 0 0 B13 0 0 0 0 0 0 0 0 B12 1 1 1 1 1 1 1 1 B11 0 0 0 0 0 0 0 0 B10 0 0 0 0 1 1 1 1 B9 0 0 1 1 0 0 1 1 B8 0 1 0 1 0 1 0 1 B7 ATL7 ATR7 ATLD REV RSV RSV RSV RSV B6 ATL6 ATR6 FMT2 ATS1 SRST RSV RSV RSV B5 ATL5 ATR5 FMT1 ATS0 DSD RSV RSV RSV B4 ATL4 ATR4 FMT0 OPE DFTH RSV RSV ID4 B3 ATL3 ATR3 DMF1 ZOE MONO RSV RSV ID3 B2 ATL2 ATR2 DMF0 DFMS CHSL DZ1 RSV ID2 B1 ATL1 ATR1 DME FLT OS1 DZ0 ZFGR ID1 B0 ATL0 ATR0 MUTE INZD OS0 PCMZ ZFGL ID0
Register Definitions
B15 Register 16 Register 17 R/W R/W B14 0 0 B13 0 0 B12 1 1 B11 0 0 B10 0 0 B9 0 0 B8 0 1 B7 ATL7 B6 ATL6 B5 ATL5 B4 ATL4 B3 ATL3 ATR3 B2 ATL2 ATR2 B1 ATL1 ATR1 B0 ATL0 ATR0
ATR7 ATR6
ATR5 ATR4
R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATx[7:0]: Digital Attenuation Level Setting These bits are available for read and write. Default value: 1111 1111b Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to -120 dB, in 0.5-dB steps. Alternatively, the attenuator can be set to infinite attenuation (or mute). The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control register 18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The attenuation level can be set using the following formula:
Attenuation level (dB) = 0.5 dB * (ATx[7:0] DEC - 255) where ATx[7:0]DEC = 0 through 255 For ATx[7:0]DEC = 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuation levels for various settings: ATx[7:0] 1111 1111b 1111 1110b 1111 1101b L 0001 0000b 0000 1111b 0000 1110b L 0000 0000b
22
Decimal Value 255 254 253 L 16 15 14 L 0
Attenuation Level Setting 0 dB, no attenuation (default) -0.5 dB -1.0 dB L -119.5 dB -120.0 dB Mute L Mute
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B15 Register 18 R/W
B14 0
B13 0
B12 1
B11 0
B10 0
B9 1
B8 0
B7 ATLD
B6 FMT2
B5 FMT1
B4 FMT0
B3
B2
B1 DME
B0 MUTE
DMF1 DMF0
R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATLD: Attenuation Load Control This bit is available for read and write. Default value: 0
ATLD = 0 ATLD = 1
Attenuation control disabled (default) Attenuation control enabled
The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD = 0, the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and 17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally. FMT[2:0]: Audio Interface Data Format These bits are available for read and write. Default value: 101 For the external digital filter interface mode (DFTH mode), this register is operated as shown in the Application for Interfacing With an External Digital Filter section of this data sheet.
FMT[2:0] 000 001 010 011 100 101 110 111
Audio Data Format Selection 16-bit standard format, right-justified data 20-bit standard format, right-justified data 24-bit standard format, right-justified data 24-bit MSB-first, left-justified data 16-bit I2S-format data 24-bit I2S-format data (default) Reserved Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface. DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function These bits are available for read and write. Default value: 00
DMF[1:0] 00 01 10 11
De-Emphasis Sampling Frequency Selection Disabled (default) 48 kHz 44.1 kHz 32 kHz
The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is enabled by setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. For the DSD mode, analog FIR filter performance can be selected using this register. Filter response plots are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. A register map is shown in the Configuration for the DSD Interface Mode section of this data sheet.
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DME: Digital De-Emphasis Control This bit is available for read and write. Default value: 0
DME = 0 DME = 1
De-emphasis disabled (default) De-emphasis enabled
The DME bit is used to enable or disable the de-emphasis function for both channels. MUTE: Soft Mute Control This bit is available for read and write. Default value: 0
MUTE = 0 MUTE = 1
MUTE disabled (default) MUTE enabled
The MUTE bit is used to enable or disable the soft mute function for both channels. Soft mute is operated as a 256-step attenuator. The speed for each step to - dB (mute) is determined by the attenuation rate selected in the ATS register.
B15 Register 19 R/W B14 0 B13 0 B12 1 B11 0 B10 0 B9 1 B8 1 B7 REV B6 ATS1 B5 ATS0 B4 OPE B3 ZOE B2 DFMS B1 FLT B0 INZD
R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 REV: Output Phase Reversal This bit is available for read and write. Default value: 0
REV = 0 REV = 1
Normal output (default) Inverted output
The REV bit is used to invert the output phase for both channels. ATS[1:0]: Attenuation Rate Select These bits are available for read and write. Default value: 00
ATS[1:0] 00 01 10 11
Attenuation Rate Selection PLRCK/2 (default) PLRCK/4 PLRCK/8 PLRCK/16
The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level transitions.
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OPE: DAC Operation Control This bit is available for read and write. Default value: 0
OPE = 0 OPE = 1
DAC operation enabled (default) DAC operation disabled
The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces them to the bipolar zero level (BPZ) even if digital audio data is present on the input. ZOE: Zero Flag Pin Operation Control This bit is available for read and write. Default value: 0
ZOE = 0 ZOE = 1
DSD data input (default) Zero flag output
The ZOE bit is used to change the DSDL (pin 1) and DSDR (pin 2) pin assignments. When the ZOE bit is set to 0, DSDL and DSDR are inputs for L-channel and R-channel data. When the ZOE bit is set to 1, DSDL and DSDR become outputs for the L-channel and R-channel zero flags, respectively. See the PCMZ and DZ[1:0] bit descriptions of register 21. DFMS: Stereo DF Bypass Mode Select This bit is available for read and write. Default value: 0
DFMS = 0 DFMS = 1
Monaural (default) Stereo input enabled
The DFMS bit is used to enable stereo operation in DF bypass mode. In the DF bypass mode, when DFMS is set to 0, the pin for the input data is PDATA (pin 5) only, therefore the DSD1792A operates as a monaural DAC. When DFMS is set to 1, the DSD1792A can operate as a stereo DAC with inputs of input L-channel and R-channel data on DSDL (pin 1) and DSDR (pin 2), respectively. FLT: Digital Filter Rolloff Control This bit is available for read and write. Default value: 0
FLT = 0 FLT = 1
Sharp rolloff (default) Slow rolloff
The FLT bit is used to select the digital filter rolloff characteristic. The filter responses for these selections are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. INZD: Infinite Zero Detect Mute Control This bit is available for read and write. Default value: 0
INZD = 0 INZD = 1
Infinite zero detect mute disabled (default) Infinite zero detect mute enabled
The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to 1 forces muted analog outputs to hold a bipolar zero level when the DSD1792A detects zero data in both channels continuously for 1024 sampling periods (1/fS). The infinite zero detect mute function is not available in the DSD mode.
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B15 Register 20 R/W
B14 0
B13 0
B12 1
B11 0
B10 1
B9 0
B8 0
B7 RSV
B6 SRST
B5 DSD
B4 DFTH
B3 MONO
B2 CHSL
B1 OS1
B0 OS0
R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 SRST: System Reset Control This bit is available for write only. Default value: 0
SRST = 0 SRST = 1
Normal operation (default) System reset operation (generate one reset pulse)
The SRST bit is used to reset the DSD1792A to the initial system condition. DSD: DSD Interface Mode Control This bit is available for read and write. Default value: 0
DSD = 0 DSD = 1
DSD interface mode disabled (default) DSD interface mode enabled
The DSD bit is used to enable or disable the DSD interface mode. DFTH: Digital Filter Bypass (or Through Mode) Control This bit is available for read and write. Default value: 0
DFTH = 0 DFTH = 1
Digital filter enabled (default) Digital filter bypassed for external digital filter
The DFTH bit is used to enable or disable the external digital filter interface mode. MONO: Monaural Mode Selection This bit is available for read and write. Default value: 0
MONO = 0 MONO = 1
Stereo mode (default) Monaural mode
The MONO function is used to change the operation mode from the normal stereo mode to the monaural mode. When the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel selection is available for L-channel or R-channel data, determined by the CHSL bit as described immediately following. CHSL: Channel Selection for Monaural Mode This bit is available for read and write. Default value: 0 This bit is available when MONO = 1.
CHSL = 0 CHSL = 1
L-channel selected (default) R-channel selected
The CHSL bit selects L-channel or R-channel data to be used in monaural mode.
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OS[1:0]: Delta-Sigma Oversampling Rate Selection These bits are available for read and write. Default value: 00
OS[1:0] 00 01 10 11
Operation Speed Select 64 times fS (default) 32 times fS 128 times fS Reserved
The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example, programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128 fS oversampling rate is not available at sampling rates above 100 kHz. If the 128 fS oversampling rate is selected, a system clock of more than 256 fS is required. In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter.
B15 Register 21 R/W B14 0 B13 0 B12 1 B11 0 B10 1 B9 0 B8 1 B7 RSV B6 RSV B5 RSV B4 RSV B3 RSV B2 DZ1 B1 DZ0 B0 PCMZ
R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 DZ[1:0]: DSD Zero Output Enable These bits are available for read and write. Default value: 00
DZ[1:0] 00 01 1x
Zero Output Enable Disabled (default) Even pattern detect 96H pattern detect
The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode. The DSD1792A sets zero flags when the 1 and 0 data are even in every 8 bits of DSD input data, or the DSD input data is 1001 0110 continuously for 200 ms. PCMZ: PCM Zero Output Enable These bits are available for read and write. Default value: 1
PCMZ = 0 PCMZ = 1
PCM zero output disabled PCM zero output enabled (default)
The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode. The DSD1792A sets the zero flags when the input data is continuously zero for 1024 LRCKs in the PCM mode or 1024 x 8 WCKs in the external filter mode.
B15 Register 22 R B14 0 B13 0 B12 1 B11 0 B10 1 B9 1 B8 0 B7 RSV B6 RSV B5 RSV B4 RSV B3 RSV B2 RSV B1 ZFGR B0 ZFGL
R: Read Mode Select Value is always 1, specifying the readback mode.
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ZFGx: Zero-Detection Flag Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback. Default value: 00
ZFGx = 0 ZFGx = 1
Not zero Zero detected
When the DSD1792A detects that audio input data is continuously zero, the ZFGx bit is set to 1 for the corresponding channel(s).
B15 Register 23 R B14 0 B13 0 B12 1 B11 0 B10 1 B9 1 B8 1 B7 RSV B6 RSV B5 RSV B4 ID4 B3 ID3 B2 ID2 B1 ID1 B0 ID0
R: Read Mode Select Value is always 1, specifying the readback mode. ID[4:0]: Device ID The ID[4:0] bits show a device ID in the TDMCA mode.
TYPICAL CONNECTION DIAGRAM IN PCM MODE
5V 0.1 F DSD Audio Data Source 1 2 3 4 PCM Audio Data Source 5 6 7 0.1 F 8 9 DSDL DSDR DBCK PLRCK PDATA PBCK SCK DGND VDD DSD1792A VCC2L AGND3L 28 27 + 10 F - + Cf Rf 5V - + + 47 F 10 k 19 18 17 16 15 + 3.3 V + 10 F 10 F 0.1 F - + Cf 5V - + Rf Differential to Single Converter With Low-Pass Filter 47 F + 10 F + Cf Rf Differential to Single Converter With Low-Pass Filter Cf Rf
IOUTL- 26 IOUTL+ AGND2 VCC1 VCOML VCOMR IREF AGND1 IOUTR- IOUTR+ AGND3R VCC2R 25 24 23 22 21 20
VOUT L-Channel
10 MS 11 MDI Controller 12 MC 13 MDO 14 RST
VOUT R-Channel
Figure 32. Typical Application Circuit for Standard PCM Audio Operation
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APPLICATION INFORMATION
APPLICATION CIRCUIT The design of the application circuit is important in order to actually realize the high S/N ratio of which the DSD1792A is capable. This is because noise and distortion that are generated in an application circuit are not negligible. In the circuit of Figure 33, the output level is 2 V rms and 127 dB S/N is achieved. The circuit of Figure 34 can realize the highest performance. In this case the output level is set to 4.5 V rms and 129 dB S/N is achieved (stereo mode). In monaural mode, if the output of the L-channel and R-channel is used as a balanced output, 132 dB S/N is achieved (see Figure 36). Figure 35 shows a circuit for the DSD mode, which is a 4th-order LPF in order to reduce the out-of-band noise. I/V Section The current of the DSD1792A on each of the output pins (IOUTL+, IOUTL-, IOUTR+, IOUTR-) is 7.8 mA p-p at 0 dB (full scale). The voltage output level of the I/V converter (Vi) is given by following equation: Vi = 7.8 mA p-p x Rf (Rf : feedback resistance of I/V converter) An NE5534 op amp is recommended for the I/V circuit to obtain the specified performance. Dynamic performance such as the gain bandwidth, settling time, and slew rate of the op amp affects the audio dynamic performance of the I/V section. Differential Section The DSD1792A voltage outputs are followed by differential amplifier stages, which sum the differential signals for each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function. The op amp recommended for the IV circuit is the NE5534, and the op amp recommended for the differential circuit is the Linear Technology LT1028, because their input noise is low.
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C1 2200 pF
R1 750 VCC VCC C11 0.1 F C17 22 pF 5 - + 4 8 6 U1 NE5534 C12 0.1 F VEE C2 2200 pF R4 560 R3 560 C3 2700 pF
R5 270
C15 0.1 F C19 33 pF 5 - + 4 U3 LT1028 C16 0.1 F VEE 6 R7 100
7 IOUT- 2 3
7 2 3
R6 270
C4 2700 pF
R2 750 VCC
C13 0.1 F C18 22 pF 5 - + 4 8 6 U2 NE5534 C14 0.1 F VEE
7 IOUT+ 2 3
VCC = 15 V VEE = -15 V fC = 217 kHz
Figure 33. Measurement Circuit for PCM, VOUT = 2 V rms
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C1 2200 pF
R1 820 VCC VCC C11 0.1 F C17 22 pF 5 - + 4 8 6 U1 NE5534 C12 0.1 F VEE C2 2200 pF R4 360 R3 360 C3 2700 pF
R5 360
C15 0.1 F C19 33 pF 5 - + 4 U3 LT1028 C16 0.1 F VEE 6 R7 100
7 IOUT- 2 3
7 2 3
R6 360
C4 2700 pF
R2 820 VCC VCC = 15 V VEE = -15 V fC = 162 kHz
C13 0.1 F C18 22 pF 5 - + 4 8 6 U2 NE5534 C14 0.1 F VEE
7 IOUT+ 2 3
Figure 34. Measurement Circuit for PCM, VOUT = 4.5 V rms
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C1 2200 pF
R1 820 VCC VCC C11 0.1 F C17 22 pF 5 - + 4 8 6 U1 NE5534 C12 0.1 F VEE C2 2200 pF R4 110 R3 110 R8 220 C3 18000 pF R9 220 C5 10000 pF
R5 330
C15 0.1 F C19 33 pF 5 - + 4 U3 LT1028 C14 0.1 F VEE 6 R7 100
7 IOUT- 2 3
R10 68 C4 47000 pF R11 68 C6 10000 pF
7 2 3
R6 330
R2 820 VCC VCC = 15 V VEE = -15 V fC = 38 kHz
C13 0.1 F C18 22 pF 5 - + 4 8 6 U2 NE5534 C14 0.1 F VEE
7 IOUT+ 2 3
Figure 35. Measurement Circuit for DSD
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IOUTL- (Pin 26) IOUTL+ (Pin 25)
IOUT- Figure 34 Circuit IOUT+
OUT+
3 1
2 IOUTR- (Pin 18) IOUTR+ (Pin 17) IOUT- Figure 34 Circuit IOUT+ OUT- Balanced Out
Figure 36. Measurement Circuit for Monaural Mode
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DFMS = 0 External Filter Device 1 2 3 WDCK (Word Clock) DATA BCK SCK 4 5 6 7 DSDL DSDR DBCK PLRCK PDATA PBCK SCK DSD1792A
DFMS = 1 External Filter Device DATA_L DATA_R 1 2 3 WDCK (Word Clock) 4 5 BCK SCK 6 7 DSDL DSDR DBCK PLRCK PDATA PBCK SCK DSD1792A
Figure 37. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
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Application for Interfacing With an External Digital Filter For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it can provide improved stop-band attenuation when compared to the internal digital filter of the DSD1792A. The DSD1792A supports several external digital filters, including:
D Texas Instruments DF1704 and DF1706 D Pacific Microsonics PMD200 HDCD filter/decoder IC D Programmable digital signal processors
The external digital filter application mode is accessed by programming the following bits in the corresponding control register:
D DFTH = 1 (register 20)
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of Figure 37. The word (WDCK) signal must be operated at 8x or 4x the desired sampling frequency, fS. System Clock (SCK) and Interface Timing The DSD1792A in an application using an external digital filter requires the synchronization of WDCK and the system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATAL, and DATAR is shown in Figure 39. Audio Format The DSD1792A in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit, and 24-bit audio data, as shown in Figure 38. The audio format is selected by the FMT[2:0] bits of control register 18.
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DSD1792A
www.ti.com SLES106 - FEBRUARY 2004 1/4 fS or 1/8 fS WDCK
BCK
Audio Data Word = 16-Bit DATA 15 16 1 2 3 MSB Audio Data Word = 20-Bit DATA 19 20 1 2 3 MSB Audio Data Word = 24-Bit DATA 23 24 1 2 3 MSB 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LSB 4 5 6 7 8 9 10 11 12 13 14 15 16 LSB
Figure 38. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
WDCK (LRCK) t(BCH) BCK t(BCY) DATA t(DS) PARAMETER t(BCY) BCK pulse cycle time t(BCL) BCK pulse duration, LOW t(BCH) BCK pulse duration, HIGH t(BL) BCK rising edge to WDCK falling edge t(LB) t(DS) t(DH) WDCK falling edge to BCK rising edge DATA setup time DATA hold time t(DH) MIN 20 7 7 5 5 5 5 MAX UNITS ns ns ns ns ns ns ns t(BL) 50% of VDD t(BCL) t(LB) 50% of VDD
50% of VDD
Figure 39. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
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Functions Available in the External Digital Filter Mode The external digital filter mode allows access to the majority of the DSD1792A mode control functions. The following table shows the register mapping available when the external digital filter mode is selected, along with descriptions of functions which are modified when using this mode selection.
B15 Register 16 Register 17 Register 18 Register 19 Register 20 Register 21 R/W R/W R/W R/W R/W R/W B14 0 0 0 0 0 0 B13 0 0 0 0 0 0 B12 1 1 1 1 1 1 B11 0 0 0 0 0 0 B10 0 0 0 0 1 1 B9 0 0 1 1 0 0 B8 0 1 0 1 0 1 0 B7 - - - REV - - - B6 - - FMT2 - SRST - - B5 - - FMT1 - 0 - - B4 - - FMT0 OPE 1 - - B3 - - - - MONO - - B2 - - - DFMS CHSL - - B1 - - - - OS1 - ZFGR B0 - - - INZD OS0 PCMZ ZFGL
Register 22 R 0 0 1 0 1 1 NOTE: 1: Bit is required for selection of external digital filter mode. -: Function is disabled. No operation even if data bit is set
FMT[2:0]: Audio Data Format Selection Default value: 000 FMT[2:0] 000 001 010 Other Audio Data Format Select 16-bit right-justified format (default) 20-bit right-justified format 24-bit right-justified format N/A
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection Default value: 00 OS[1:0] 00 01 10 11 Operation Speed Select 8 times WDCK (default) 4 times WDCK 16 times WDCK Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter and the delta-sigma modulator. For example, if the external digital filter is 8x oversampling, and the user selects OS[1:0] = 00, then the delta-sigma modulator oversamples by 8x, resulting in an effective oversampling rate of 64x. The 16x WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected is 16x WDCK, the system clock frequency must be over 256 fS.
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APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
DSD Decoder DATA_L DATA_R Bit Clock DSDL DSDR DBCK PLRCK PDATA PBCK SCK DSD1792A
1 2 3 4 5 6 System Clock (1) 7
(1) The system clock can be removed after setting the register to the DSD mode.
Figure 40. Connection Diagram in DSD Mode Feature This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD) applications. The DSD mode is accessed by programming the following bit in the corresponding control register. DSD = 1 (register 20) The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure. Four FIR responses are available and are selected by the DMF[1:0] bits of control register 18.
Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan. 37
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Pin Assignment When DSD Format Interface Several pins are redefined for DSD mode operation. These include:
D DSDL (pin 1): DATAL as L-channel DSD data input D DSDR (pin 2): DATAR as R-channel DSD data input D DBCK (pin 3): Bit clock (BCK) for DSD data
t = 1/(64 x 44.1 kHz)
DBCK
DSDL DSDR
D0
D1
D2
D3
D4
Figure 41. Normal Data Output Form From DSD Decoder
t(BCH) DBCK t(BCY) DSDL DSDR t(DS)
t(BCL) 50% of VDD
50% of VDD t(DH) PARAMETER MIN 85(1) 30 30 10 10 MAX UNITS ns ns ns ns ns
t(BCY) DBCK pulse cycle time t(BCH) DBCK high-level time t(BCL) DBCK low-level time t(DS) DSDL, DSDR setup time t(DH) DSDL, DSDR hold time (1) 2.8224 MHz x 4. (2.8224 MHz = 64 x 44.1 kHz. This value is specified as a sampling rate of DSD.)
Figure 42. Timing for DSD Audio Interface
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ANALOG FIR FILTER PERFORMANCE IN DSD MODE
GAIN vs FREQUENCY
0 0 fc = 185 kHz Gain(1) = -6.6 dB -1 -10
GAIN vs FREQUENCY
-2 Gain - dB Gain - dB 0 50 100 f - Frequency - kHz 150 200
-20
-3
-30
-4
-40
-5
-50
-6
-60 0 500 1000 1500 f - Frequency - kHz
Figure 43. DSD Filter-1, Low BW
GAIN vs FREQUENCY
0 0
Figure 44. DSD Filter-1, High BW
GAIN vs FREQUENCY
fc = 77 kHz Gain(1) = -6 dB
-1
-10
-2 Gain - dB Gain - dB 0 50 100 f - Frequency - kHz 150 200
-20
-3
-30
-4
-40
-5
-50
-6
-60 0 500 1000 1500 f - Frequency - kHz
Figure 45. DSD Filter-2, Low BW
Figure 46. DSD Filter-2, High BW
(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz x 64 fS), and 50% modulation DSD data input, unless otherwise noted. 39
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GAIN vs FREQUENCY
0 0
GAIN vs FREQUENCY
fc = 85 kHz Gain(1) = -1.5 dB
-1
-10
-2 Gain - dB Gain - dB
-20
-3
-30
-4
-40
-5
-50
-6 0 50 100 f - Frequency - kHz 150 200
-60 0 500 1000 1500 f - Frequency - kHz
Figure 47. DSD Filter-3, Low BW
Figure 48. DSD Filter-3, High BW
GAIN vs FREQUENCY
0 0
GAIN vs FREQUENCY
fc = 94 kHz Gain(1) = -3.3 dB
-1
-10
-2 Gain - dB Gain - dB 0 50 100 f - Frequency - kHz 150 200
-20
-3
-30
-4
-40
-5
-50
-6
-60 0 500 1000 1500 f - Frequency - kHz
Figure 49. DSD Filter-4, Low BW
Figure 50. DSD Filter-4, High BW
(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
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DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode DSD = 1 (Register 20, B5)
B15 Register 16 Register 17 Register 18 Register 19 Register 20 Register 21 R/W R/W R/W R/W R/W R B14 0 0 0 0 0 0 B13 0 0 0 0 0 0 B12 1 1 1 1 1 1 B11 0 0 0 0 0 0 B10 0 0 0 0 1 1 B9 0 0 1 1 0 0 B8 0 1 0 1 0 1 0 B7 - - - REV - - - B6 - - - - SRST - - B5 - - - - 1 - - B4 - - - OPE - - - B3 - - DMF1 - MONO - - B2 - - DMF0 - CHSL DZ1 - B1 - - - - OS1 DZ0 ZFGR B0 - - - - OS0 - ZFGL
Register 22 R 0 0 1 0 1 1 : -: Function is disabled. No operation even if data bit is set NOTE
DMF[1:0]: Analog FIR Performance Selection Default value: 00 DMF[1:0] 00 01 10 11 Analog-FIR Performance Select FIR-1 (default) FIR-2 FIR-3 FIR-4
Plots for the four analog FIR filter responses are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. OS[1:0]: Analog-FIR Operation-Speed Selection Default value: 00 OS[1:0] 00 01 10 11 Operation Speed Select fDBCK (default) fDBCK/2 Reserved fDBCK/4
The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before setting the DSD bit to 1. Requirements for System Clock The bit clock (BCK) for the DSD mode is required at pin 3 of the DSD1792A. The frequency of the bit clock can be N times the sampling frequency. Generally, N is 64 in DSD applications. The interface timing between the bit clock and DATAL and DATAR is required to meet the same setup- and hold-time specifications as shown for the audio interface timing in Figure 42.
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TDMCA Format The DSD1792A supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the host control serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for any programmable devices. The TDMCA format can transfer not only audio data but also command data, so that it can be used together with any kind of device that supports the TDMCA format. The TDMCA frame consists of command field, extended command field, and some audio data fields. Those audio data are transported to IN devices (such as a DAC) and/or from OUT devices (such as an ADC). The DSD1792A is an IN device. LRCK and BCK are used with both IN and OUT devices so that the sample frequency of all devices in a system must be the same. The TDMCA mode supports a maximum of 30 device IDs. The maximum number of audio channels depends on the BCK frequency. TDMCA Mode Determination The DSD1792A recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse duration of two BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%. Figure 51 shows the LRCK and BCK timing that determines the TDMCA mode. The DSD1792A enters the TDMCA mode after two continuous TDMCA frames. Any TDMCA commands can be issued during the next TDMCA frame after the TDMCA mode is entered.
Pre-TDMCA Frame LRCK TDMCA Frame Command Accept
2 BCK
BCK
Figure 51. LRCK and BCK Timing of Determination TDMCA Mode TDMCA Terminals TDMCA requires six signals, of which four signals are for command and audio data interface, and one pair is for daisy chaining. Those signals can be shared as in the following table. The DO signal has a 3-state output so that it can be connected directly to other devices.
TERMINAL NAME PLRCK PBCK PDATA MDO MC MS TDMCA NAME LRCK BCK DI DO DCI DCO I/O I I I O I O DESCRIPTION TDMCA frame start signal. It must be the same as the sampling frequency. TDMCA clock. Its frequency must be high enough to communicate a TDMCA frame within an LRCK cycle. TDMCA command and audio data input signal TDMCA command data 3-state output signal TDMCA daisy-chain input signal TDMCA daisy-chain output signal
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Device ID Determination The TDMCA mode also supports a multichip implementation in one system. This means a host controller (DSP) can simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM devices. The PCM devices are categorized as IN device, OUT device, IN/OUT device, and NO device. The IN device has an input port to get audio data, the OUT device has an output port to supply audio data, the IN/OUT device has both input and output ports for audio data, and the NO device has no port for audio data but needs command data from the host. A DAC is an IN device, an ADC is an OUT device, a CODEC is an IN/OUT device, and a PLL is a NO device. The DSD1792A is an IN device. For the host controller to distinguish the devices, each device is assigned its own device ID by the daisy chain. The devices obtain their own device IDs automatically by connecting their DCI to the DCO of the preceding device and their DCO to the DCI of the following device in the daisy chain. The daisy chains are categorized as the IN chain and the OUT chain, which are completely independent and equivalent. Figure 52 shows an example daisy-chain connection. If a system needs to chain the DSD1792A and a NO device in the same IN or OUT chain, the NO device should be chained at the back end of the chain because it does not require any audio data. Figure 53 shows an example of TDMCA system including an IN chain and an OUT chain with a TI DSP. For a device to get its own device ID, the DID signal must be set to 1 (see the Command Field section for details), and LRCK and BCK must be driven in the TDMCA mode for all PCM devices which are chained. The device at the top of the chain knows its device ID is 1 because its DCI is fixed HIGH. Other devices count the BCK pulses and observe their own DCI signal to determine their position and ID. Figure 54 shows the initialization of each device ID.
IN Chain
DCI
DCI
DCI
DCOi
DCOi
DCO
DCO
DCO
DCI
***
IN Device
IN Device
IN IN/OUT Device
IN
***
NO Device
NO Device
***
DCOo
IN/OUT Device OUT DCIo DCOo NO Device DCO DCI NO Device DCO 43 DCI
OUT Device DCO DCI
OUT Device DCIo DCO DCI
***
OUT
***
OUT Chain
Figure 52. Daisy-Chain Connection
DCO
DCIi
DCIi
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DCII LRCK BCK DI DCOI DO DCOO Device ID = 1 IN/OUT Device (DIX1700) DCIO
LRCK BCK DI DO
IN Device (DSD1792A)
DCI
DCO Device ID = 2
LRCK BCK DI DO
NO Device
DCI
DCO Device ID = 3
* * *
FSX FSR CLKX CLKR DX DR TI DSP LRCK BCK DI DO DCO Device ID = 3 OUT Device DCI LRCK BCK DI DO DCO Device ID = 2 OUT Device DCI
* * * Figure 53. IN Daisy-Chain and OUT Daisy-Chain Connection for a Multichip System
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LRCK BCK
DI
DID
Command Field
Device ID = 1 Device ID = 2
DCO1 DCO1 DCI2
DCO2 DCI3 * * * * * * Device ID = 30 DCO29 DCI30
Device ID = 3
58 BCK
Figure 54. Device ID Determination Sequence TDMCA Frame In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields. All of them are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each field. The command field is always transferred as the first packet of the frame. The EMD field is transferred if the EMD flag of the command field is HIGH. If any EMD packets are transferred, no audio data follows the EMD packets. This frame is for quick system initialization. All devices of a daisy chain should respond to the command field and extended command field. The DSD1792A has two audio channels that can be selected by OPE (register 19). If the OPE bit is not set HIGH, those audio channels are transferred. Figure 55 shows the general TDMCA frame. If some DACs are enabled, but corresponding audio data packets are not transferred, the analog outputs are unpredictable.
1/fS LRCK BCK [For Initialization] DI CMD 32 Bits DO [For Operation] DI CMD Ch1 Ch2 Ch3 Ch4 Ch(n)
Don't Care
EMD
EMD
EMD
EMD
EMD
Don't Care
CMD
CMD
CMD
CMD
CMD
CMD
CMD
CMD
DO
CMD
Ch1
Ch2
Ch3
Ch4
Ch(m)
Figure 55. General TDMCA Frame
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1/fS (256 BCK Clocks) 7 Packets x 32 Bits LRCK BCK
DI
CMD
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Don't Care
CMD
IN and OUT Channel Orders are Completely Independent DO
CMD
Ch1
Ch2
Figure 56. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read Command Field The normal command field is defined as follows. When the DID bit (MSB) is 1, this frame is used only for device ID determination, and all remaining bits in the field are ignored.
31 command DID 30 EMD 29 DCS 28 24 23 R/W 22 register ID 16 15 data 8 7 not used 0 device ID
Bit 31: Device ID enable flag The DSD1792A operates to get its own device ID for TDMCA initialization if this bit is HIGH. Bit 30: Extended command enable flag EMD packet is transferred if this bit is HIGH, otherwise skipped. Once this bit is HIGH, this frame does not contain any audio data. This is for system initialization. Bit 29: Daisy-chain selection flag HIGH designates OUT-chain devices, LOW designates IN-chain devices. The DSD1792A is an IN device, so the DCS bit must be set to LOW. Bits[28:24]: Device ID. It is 5 bits length, and it can be defined. These bits identify the order of a device in the IN or OUT daisy chain. The top of the daisy chain defines device ID 1 and successive devices are numbered 2, 3, 4, etc. All devices for which the DCI is fixed HIGH are also defined as ID 1. The maximum device ID is 30 each in the IN and OUT chains. If a device ID of 0x1F is used, all devices are selected as broadcast when in the write mode. If a device ID of 0x00 is used, no device is selected. Bit 23: Command Read/Write flag If this bit is HIGH, the command is a read operation. Bits[22:16]: Register ID It is 7 bits in length. Bits[15:8]: Command data It is 8 bits in length. Any valid data can be chosen for each register. Bits[7:0]: Not used These bits are never transported when a read operation is performed. Extended command field The extended command field is the same as the command field, except that it does not have a DID flag.
31 extended command rsvd 30 EMD 29 DCS 28 24 23 R/W 22 register ID 16 15 data 8 7 not used 0 device ID
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Audio Fields The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed with 0s as shown in the following example.
31 audio data MSB 16 24 bits 12 8 LSB 7 43 All 0s 0
TDMCA Register Requirements TDMCA mode requires device ID and audio channel information, previously described. The OPE bit in register 19 indicates audio channel availability and register 23 indicates the device ID. Register 23 is used only in the TDMCA mode. See the mode control register map (Table 3). Register Write/Read Operation The command supports register write and read operations. If the command requests to read one register, the read data is transferred on DO during the data phase of the timing cycle. The DI signal can be retrieved at the positive edge of BCK, and the DO signal is driven at the negative edge of BCK. DO is activated one BCK cycle early to compensate for the output delay caused by high impedance. Figure 57 shows the TDMCA write and read timing.
Register ID Phase Data Phase
BCK
DI
Read Mode and Proper Register ID
Write Data Retrieved, if Write Mode
DO
Read Data Driven, if Read Mode 1 BCK Early
DOEN (Internal)
Figure 57. TDMCA Write and Read Operation Timing TDMCA-Mode Operation DCO specifies the owner of the next audio channel in TDMCA-mode operation. When a device retrieves its own audio channel data, DCO goes HIGH during the last audio channel period. Figure 58 shows the DCO output timing in TDMCA-mode operation. The host controller ignores the behavior of DCI and DCO. DCO indicates the last audio channel of each device. Therefore, DCI means the next audio channel is allocated. If some devices are skipped due to no active audio channel, the skipped devices must notify the next device that the DCO will be passed through the next DCI. Figure 59 and Figure 60 show DCO timing with skip operation. Figure 61 shows the ac timing of the daisy-chain signals.
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1/fS (384 BCK Clocks) 9 Packets x 32 Bits LRCK BCK IN Daisy Chain DI DCI1 DID = 1 DID = 2 DID = 3 DID = 4 DCO1 DCI2 DCO2 DCI3 DCO3 DCI4 DCO4 CMD Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Don't Care CMD
Figure 58. DCO Output Timing of TDMCA Mode Operation
1/fS (256 BCK Clocks) 5 Packets x 32 Bits
LRCK BCK
DI
CMD
Ch1
Ch2
Ch15
Ch16
Don't Care
CMD
DCI DID = 1 DCO DCI DID = 2 * * * * * * DID = 8 DCO DCO * * * DCI 14 BCK Delay 2 BCK Delay
Figure 59. DCO Output Timing With Skip Operation
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Command Packet
LRCK
BCK DID EMD
DI
DCO1
DCO2 * * *
Figure 60. DCO Output Timing With Skip Operation (for Command Packet 1)
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LRCK
t(LB) BCK
t(BL)
t(BCY) DI
t(DS)
t(DH)
t(DOE)
DO
t(DS) DCI
t(DH)
t(COE) DCO
PARAMETER t(BCY) BCK pulse cycle time t(LB) LRCK setup time t(BL) t(DS) t(DH) t(DS) LRCK hold time DI setup time DI hold time DCI setup time
MIN 20 0 3 0 3 0 3
MAX
UNITS ns ns ns ns ns ns ns
t(DH) DCI hold time t(DOE) DO output delay(1) t(COE) DCO output delay(1) (1) Load capacitance is 10 pF.
8 6
ns ns
Figure 61. AC Timing of Daisy-Chain Signals
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THEORY OF OPERATION
Upper 6 Bits ICOB Decoder 0-62 Level 0-66 Advanced DWA 0-4 Level Current Segment DAC Analog Output
Digital Input 24 Bits 8 fS MSB and Lower 18 Bits 3rd-Order 5-Level Sigma-Delta
Figure 62. Advanced Segments DAC The DSD1792A uses TI's advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1792A provides balanced voltage outputs. Digital input data via the digital filter is separated into six upper bits and 18 lower bits. The six upper bits are converted to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are processed by a five-level third-order delta-sigma modulator operated at 64 fS by default. The 1 level of the modulator is equivalent to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order delta-sigma modulator are summed together to an up to 66-level digital code, and then processed by data-weighted averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is converted to an analog output in the differential-current segment section. This architecture has overcome the various drawbacks of conventional multibit processing and also achieves excellent dynamic performance.
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Analog output The following table and Figure 63 show the relationship between the digital input code and analog output.
800000 (-FS) IOUTN [mA] IOUTP [mA] VOUTN [V] VOUTP [V] -2.3 -10.1 -1.725 -7.575 000000 (BPZ) -6.2 -6.2 -4.650 -4.650 7FFFFF (+FS) -10.1 -2.3 -7.575 -1.725
VOUT [V] -2.821 0 2.821 : VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the NOTE application circuit of Figure 33.
OUTPUT CURRENT vs INPUT CODE
0
-2 IO - Output Current - mA IOUTN -4
-6
-8 IOUTP
-10
-12 800000(-FS) 000000(BPZ) Input Code - Hex 7FFFFF(+FS)
Figure 63. The Relationship Between Digital Input and Analog Output
52
MECHANICAL DATA
MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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